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HSP48908/883
Data Sheet May 1999 File Number
2783.4
Two Dimensional Convolver
The Intersil HSP48908/883 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through the use of the on-chip row buffers which are programmable for row lengths up to 1024 pixels. There are internal register banks for storing two independent 3 x 3 filter kernels, thus, facilitating the implementation of adaptive filters and multiple filter operations on the same data. The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations. Data is provided to the HSP48908/883 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the 3 x 3 convolution operation. Images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple HSP48908/883s. Coefficient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit convolver output guarantees no overflow for kernel sizes up to 4 x 4. Larger kernel sizes can be implemented however, since the filter coefficients will normally be less than their maximum 8-bit values. The HSP48908/883 is manufactured using an advanced CMOS process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs are TTL compatible.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Single Chip 3 x 3 Kernel Convolution * Programmable On-Chip Row Buffers * DC to 27MHz Clock Rate * Cascadable for Larger Kernels and Images * On-Chip 8-Bit ALU * Dual Coefficient Mask Registers, Switchable in a Single Clock Cycle * 8-Bit Signed or Unsigned Input and Coefficient Data * 20-Bit Extended Precision Output * Standard P Interface
Applications
* Image Filtering * Edge Detection * Adaptive Filtering * Real Time Video Filter
Ordering Information
PART NUMBER HSP48908GM-20/883 HSP48908GM-27/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 84 Ld PGA 84 Ld PGA PKG. NO. CMGA3-84 CMGA3-84
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HSP48908/883 Pinouts
84 PIN PGA TOP VIEW
11
CASO6
DOUT0
DOUT1
GND
DOUT5
DOUT6
DOUT8
DOUT10 DOUT12 DOUT13 DOUT15
10
CASO4
CASO5
CASO7
DOUT2
DOUT4
DOUT9
GND
DOUT11 DOUT14
GND
DOUT17
9
CASO3
GND
DOUT3
DOUT7
VCC
DOUT16 DOUT18
8
CASO1
CASO2
DOUT19
GND
7
OE
GND
VCC
CASI1
FRAME
CASI0
6
DIN1
CASO0
DIN0
CASI2
VCC
RESET
5
DIN2
DIN3
DIN4
CASI5
CASI4
CASI3
4
DIN5
DIN6
CASI7
CASI6
3
DIN7
CIN1
CIN9
HOLD
LD
CASI10
CASI8
2
CIN0
CIN3
CIN4
CIN7
GND
VCC
A2
EALU
CASI13
CASI11
CASI9
1
CIN2 A
CIN5 B
CIN6 C
CIN8 D
CLK E
A1 F
CS G
A0 H
CASI15 J
CASI14 CASI12 K L
2
HSP48908/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied . . . . .GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . 35.0 6.0 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.45W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Die Characteristics
Number of Transistors or Gates . . . . . . . . . . . . . 190,000 Transistors
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS GROUP A SUBGROUP 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Clock Input High Clock Input Low Output HIGH Voltage
SYMBOL VIH VIL VIHC VILC VOH VOL II IO ICCSB
TEST CONDITIONS VCC = 5.5V VCC = 4.5V VCC = 5.5V VCC = 4.5V IOH = 400mA, VCC = 4.75V (Note 2) IOL = +2.0mA, VCC = 4.5V (Note 2) VIN = VCC or GND, VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open (Note 5) f = 20.0MHz, VCC = 5.5V Outputs Open, (Note 3, 5) (Notes 4, 5)
MIN 2.2 3.0 2.6
MAX 0.8 0.8 -
UNITS V V V V V
Output LOW Voltage
1, 2, 3
-
0.4
V A A A
Input Leakage Current
1, 2, 3
-10
+10
Output or I/O Leakage Current Standby Power Supply Current
1, 2, 3
-10
+10
1, 2, 3
-
500
Operating Power Supply Current
ICCOP
1, 2, 3
-55 TA 125
-
160.0
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL 1.5V, VIHC = 3.4V, and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF.
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HSP48908/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VCC = 5.0V 10%, TA = -55oC to 125oC (Note 9) -27 (27MHz) PARAMETER Clock Period Clock Pulse Width High Clock Pulse Width Low Data Input Setup Time Data Input Hold Time Clock to Data Out Address Setup Time Address Hold Time Configuration Data Setup Time Configuration Data Hold Time LD Pulse Width LD Setup Time CIN7-0 Setup to CLK CIN7-0 Hold to CLK CS Setup to LD CS Setup to LD RESET Pulse Width FRAME Setup to Clock FRAME Pulse Width EALU Setup Time EALU Hold Time HOLD Setup Time HOLD Hold Time Output Enable Time NOTES: 6. This specification applies only to the case where the HSP48908/883 is being written to during an active convolution cycle. It must be met in order to achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded asynchronously and the t LCS Specification may be disregarded. 7. While FRAME is an asynchronous signal, it must be deasserted a minimum of tFS ns prior to the rising clock edge which is to begin loading pixel data for a new frame. 8. Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with CL = 40pF. 9. AC Testing is performed as follows: Input levels (CLK input) 4.0V and 0V, input levels (all other inputs) 0V and 3.0V, timing reference levels (CLK) = 2.0V, (others) = 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured at VOH 1.5V and VOL 1.5V. SYMBOL tCYCLE tPWH tPWL tDS tDH tOUT tAS tAH tCDS tCDH tLPW tLCS tCS tCH tCSS tCSH tRPW tFS tFPW tES tEH tHS tHH tEN Note 8 Note 7 Note 6 NOTES GROUP A SUBGROUP 9, 10, 11 9, 10, 11 TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 37 15 MAX -20 (20MHz) MIN 50 20 MAX UNITS ns ns
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
15 16 0 15 0 17
19 -
20 17 0 15 0 20
28 -
ns ns ns ns ns ns ns
9, 10, 11
0
-
0
-
ns
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
15 30 17 0 0 0 37 25 37 15 0 13 2 -
19
20 37 20 0 0 0 50 30 50 17 0 14 2 -
28
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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HSP48908/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS TEMP (oC) TA = 25 -27 MIN MAX 10 MIN -20 MAX 10 UNITS pF
PARAMETERS Input Capacitance
SYMBOL C IN
CONDITIONS VCC = Open f = 1MHz, all measurements are referenced to device GND VCC = Open f = 1MHz, all measurements are referenced to device GND
NOTES 10
Output Capacitance
CO
10
TA = 25
-
12
-
12
pF
Output Disable Time Output Rise Time Output Fall Time NOTES:
t OZ tr tf From 0.8V to 2.0V From 2.0V to 0.8V
10, 11 10, 11 10, 11
-55 TA 125 -55 TA 125 -55 TA 125
-
35 6 6
-
40 6 6
ns ns ns
10. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 11. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
Test Load Circuit
S1 DUT (NOTE 12) CL IOH 1.5V IOL
EQUIVALENT CIRCUIT
NOTES: 12. Includes stray and jig capacitance. 13. Switch S1 Open for ICCSB and ICCOP Tests.
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HSP48908/883 Burn-In Circuit
11
CASO6 DOUT0 DOUT1
GND
DOUT5 DOUT6 DOUT8 DOUT10 DOUT12 DOUT13 DOUT15
10
CASO4 CASO5 CASO7 DOUT2 DOUT4 DOUT9
GND
DOUT11 DOUT14
GND
DOUT17
9
CASO3
GND
DOUT3 DOUT7
VCC
DOUT16 DOUT18
8
CASO1 CASO2
DOUT19
GND
7
OE
GND
VCC
CASI1 FRAME CASI0
6
DIN1
CASOd
DIN0
CASI2
VCC
RESET
5
DIN2
DIN3
DIN4
CASI6 CASI14 CASI13
4
DIN5
DIN6
CASI7 CASI16
3
DIN7
CIN1
CIN9
HOLD
LD
CASI10 CASI18
2
CIN0
CIN3
CIN4
CIN7
GND
VCC
A2
EALU
CASI13 CASI11 CASI9
1
CIN2
CIN5
CIN6
CIN8
CLK
A1
CS
A0
CASI15 CASI14 CASI12
A
B
C
D
E
F
G
H
J
K
L
6
HSP48908/883
PGA BURN-IN SCHEMATIC PIN NAME CIN2 CIN0 DIN7 DIN5 DIN2 DIN1 OE CASO.1 CASO.3 CASO.4 CASO.6 CIN5 CIN3 CIN1 DIN6 DIN3 CASO.0 GND CASO.2 GND CASO.5 POUT0 CIN6 CIN4 DIN4 DIN0 VCC CASO.7 NOTES: 14. VCC/2 (2.7 10%) used for outputs only. 15. 47k (20%) resistor connected to all pins except VCC and GND. 16. VCC = 5.5 0.5V. 17. 0.1F (minimum) capacitor between VCC and GND per position. 18. F0 = 100kHz 10%, F1 - F0/2, F2 = F1/2...F11 = F10/2, 40 - 60% duty cycle. 19. Input Voltage Limits: VIL = 0.8V maximum, VIH = 4.5V 10%. PGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C5 C6 C7 C10 BURN-IN SIGNAL F13 F12 F7 F5 F2 F1 F10 VCC/2 VCC/2 VCC/2 VCC/2 F12 F13 F12 F6 F3 VCC/2 GND VCC/2 GND VCC/2 VCC/2 F13 F13 F4 F0 VCC VCC/2 PIN NAME POUT1 CIN8 CIN7 POUT2 GND CLK GND CIN9 POUT3 POUT4 POUT5 A1 VCC HOLD POUT7 POUT9 POUT6 CS A2 LOAD VCC GND POUT8 A0 EALU POUT11 POUT10 CASI.15 PGA PIN C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3 F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 BURN-IN SIGNAL VCC/2 F14 F12 VCC/2 GND F0 GND F14 VCC/2 VCC/2 VCC/2 F13 VCC F14 VCC/2 VCC/2 VCC/2 F12 F14 F11 VCC GND VCC/2 F12 F8 VCC/2 VCC/2 F7 PIN NAME CASI.13 CASI.5 CASI.2 CASI.1 POUT14 POUT12 CASI.14 CASI.11 CASI.10 CASI.7 CASI.4 VCC FRAME POUT19 POUT16 GND POUT13 CASI.12 CASI.9 CASI.8 CASI.6 CASI.3 RESET CASI.0 GND POUT18 POUT17 POUT15 PGA PIN J2 J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 BURN-IN SIGNAL F5 F5 F2 F1 VCC/2 VCC/2 F6 F3 F2 F7 F4 VCC F15 VCC/2 VCC/2 GND VCC/2 F4 F1 F0 F6 F3 F16 F0 GND VCC/2 VCC/2 VCC/2
Die Characteristics
DIE DIMENSIONS: 341 mils x 322 mils x 19 mils 1 mil METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 GLASSIVATION: Type: Nitrox Thickness: 10kA
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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